1. Field of the Invention
The present invention relates generally to a low cost SRAM (Static Random Access Memory) cell with P and N well contacts and preferably with a P+ diffusion crossing to ground, and more particularly pertains to a low cost design for a SRAM cell that is complete at the M2 metal level and has improved cell passgate leakage, functionality and fabrication yields.
2. Discussion of the Prior Art
Initially, all dimensions shown in FIGS. 1, 2, 4 and 5 are in microns, and FIGS. 1 and 2 also show the dimensions in microns of the SRAM cell size.
FIG. 1 illustrates a top plan view of a circuit lay-out of a prior art 90 nm node technology SRAM cell. FIG. 1 illustrates only the PC (polysilicon conductor) areas, the RX (active silicon conductor regions which are isolated by trench isolation regions) regions, and the M1 (first metal) level of the SRAM cell and chip, and the M2 and M3 (second and third metal) levels are not shown.
FIG. 2 illustrates a simplified version of FIG. 1, and shows only the PC and RX areas and regions of the SRAM cell and chip, and the M1 metal level is not shown.
The prior art 90 nm node technology SRAM cell is fabricated in a base PC (Polysilicon Conductor) level, the overlying bottom M1 metal level, the next higher metal level M2, and the next higher metal layer M3. The prior art 90 nm node technology SRAM cell is fabricated with a PC level wordline WL having a crooked V shape at 10 and an M2 metal level bitline BL. For large SRAM arrays, the PC level is not an efficient enough conductor for the global wordlines, and the M3 metal level must be used for the global wordlines.
In summary, the PC level contains the wordlines WL, the M2 metal level contains the ground GND and the VDD power supply (which are connected through the M1 metal layer, shown in FIG. 1 as M1 GND and M1 VDD, which connect to adjacent SRAM cells) and the bitlines BL, and the M3 metal level contains the global wordlines. The prior art SRAM cell includes 8.5 CA (contacts), 2 V1 (vias), and no PW (P Well) and NW (N Well) contacts which requires that additional real estate be provided on the chip outside the circuit shown in FIG. 1 for periodic contacts to the PWs and NWs.
FIG. 3 illustrates a circuit schematic of the prior art 90 nm node technology SRAM cell. The circuit of the prior art 90 nm node technology SRAM cell is well known and includes cross coupled pnp pull-up devices P1, P2 and npn pull-down devices N1, N2, with the P1, P2 devices being connected to the power supply VDD, and the N1, N2 devices being connected directly to ground GND. The left npn passgate NL is coupled between the left bitline BL and the junction of devices P1 and N1, with its gate coupled to the wordline WL. The right npn passgate NR is coupled between the right bitline BR and the junction of devices P2 and N2, with its gate coupled to the wordline WL
Referring to FIG. 1 and more clearly to FIG. 2, the PC (Polysilicon Conductor) level WL extends horizontally across the lower portion of the chip with a V shaped dip 10 in the middle, and crosses left and right legs of a bottom M shaped N+RX (active silicon conductor) region, with the crossing on the left defining the passgate NL, with the WL defining the gate G and the RX region defining the source S and drain D regions of the passgate NL, and with the crossing on the right defining the passgate NR, with the WL defining the gate G and the RX region defining the source S and drain D regions of the passgate NR.
Left and right PC regions extend vertically on opposite left and right portions of the SRAM cell as shown in FIGS. 1 and 2.
The top horizontal portion of the bottom M shaped RX region crosses the left PC region and defines the pulldown device N1, with the left PC region defining the gate G and the RX region defining the drain D and source S regions of the pulldown device N1. The top horizontal portion of the M shaped RX region crosses the right PC region and defines the pulldown device N2, with the right PC region defining the gate G and the RX region defining the source S and drain D regions of the pulldown device N2, with a common source region S between the pulldown devices N1 and N2.
A horizontal base of a top W shaped P+RX (active silicon conductor) region crosses the upper portions of the left and right PC regions.
The bottom horizontal portion of the top W shaped RX region crosses the left PC region and defines the pullup device P1, with the left PC region defining the gate G and the RX region defining the drain D and source S regions of the pullup device P1. The bottom horizontal portion of the W shaped RX region crosses the right PC region and defines the pullup device P2, with the right PC region defining the gate G and the RX region defining the source S and drain D regions of the pullup device P2, with a common source region S between the pullup devices P1 and P2.
As illustrated in FIG. 1, the V shape of the PC level word line WL snakes around the GND contact CA 12. The PC level word line WL snaking around the GND contact 12 is the main reason for the M3 metal level global word lines, and for a 45 degree PC level slant over the passgates as shown at 10.
The prior art cell behavior becomes erratic with RX/PC mask/level misalignments.
The passgate leakage of fabricated SRAM cells has also fluctuated from lot to lot and has been excessively high in most cases.
A demand exists for low cost SRAM cells, complete at the M2 metal level, and with better control over cell passgate leakage.